International journal of computing and digital systems

Cell Optimization and Realization of Vedic Multiplier Design in QCA

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Design and Analysis of Efficient Vedic Multiplier for Fast Computing Applications

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Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ

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Design of Compensated Supply Circuit Topology for a Ring Oscillator

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True Single Phase Clock based UP-DOWN Counter using GDI Cell for Low Power Applications

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