Aunrag Yadav (PHD/19/ ECE/2461)

In the Very Large Scale Integration (VLSI) technology, many advancements are happening in the semiconductor industry, and these developments arise due to the increasing demand for battery-operated devices; these include laptops, smartphones, tablets, and many biomedical devices. There is a need for electronic components that can convert the analog signal into a digital signal, which is used to store the signals in memory and for further data processing and communication. There is an increase in demand for high-pixel cameras and high storage memory. The camera is used to capture the light and convert it into an electrical signal, and these signals get stored in the memory in digital form for further processing. To make high-pixel cameras and large storage in a limited silicon surface, there is a requirement for a large number of transistors, which increases the system complexity, leakages, and power dissipation. To maintain the limit of surface area, there is a need to reduce transistor sizes, which gives rise to short-channel effects, making the circuit design more complicated. As semiconductor technologies approach the boundaries set by Moore's Law, engineers and researchers are seeking innovative approaches to address challenges in speed, power efficiency, and propagation delay utilization encountered in modern circuit design while maintaining the performance of the electronic circuits. Electronic circuits such as analog-to-digital converters (ADCs) are very important blocks for the interface between the analog and digital world. Optimized ADCs circuit design, in terms of surface area, power dissipation and performance are paramount consideration. This optimization helps improvement in battery life of the devices and the performance of smart devices which are used in biomedical, wireless communication, digital signal processing, biomedical systems, internet of thinks (IOTs), and wireless sensor networks. There are many architectures of ADCs possible, such as delta sigma, successive approximation register (SAR), flash, and pipeline, etc. The comparator is a crucial component of an ADC. The design of the comparator heavily influences how well the ADC performs. To make high-accuracy, low power and high speed ADCs, there is requirement of low offset, low power and high speed comparators. This is used for the quantization process in ADCs and it is also used as data slicers in receivers. To create a quicker and more effective ADC, several comparator structures have been presented in recent years. Their goal is to give high speed, low power, offset and surface area for comparator circuits. Comparators come in two forms: Static and Dynamic. An operational amplifier can act as a static comparator, but they are very slow and consume excessive power. The low input voltage range and kickback noise are additional issues with these kind of comparators. To boost the speed high bandwidth is necessary, which calls for raising the input transistors' transconductance. This necessitates high aspect ratio transistors, which raises power consumption. Also, to reduce the offset it is necessary to increase the tail current and aspect ratio of the input transistors. The high kickback noise in static comparators is also a major problem that affects the comparator's input signal. The Dynamic comparators can help to tackle the problems arising with static comparators. The architecture of the dynamic comparator is divided into two parts: one is the preamplifier and the other is the latch. The clock signal serves as the foundation for the dynamic comparator's functionality. The advantage of dyanamic comparators is their low static power dissipation. While the dyanamic power dissipation incleases due to the output signal changing during the clock transition. The Latch stage in this comparator has positive feedback or regenerative latching, which helps in increasing the speed of comparators. The dynamic comprators are of various kind but here only single tail and double tail dynamic comparator designs are discussed. Single-Tail Dynamic Comparator design uses stack transistors and it operates at a high voltage. The operation of this design is typical since there is only one path for the current to travel through the amplifier and latch. They have a trade-off among power consumption, offset and speed. There is the problem of kickback noise due to the coupling of the capacitances of input transistors to the output terminals of the latch, which affects the input signals. There is one more problem, which is a large headroom due to the stacked transistors. To overcome these issues, the input stage is separated from the output stage and this architecture is known as the Double Tail Dynamic Comparator. The advantage of this kind of dynamic comparator is that it has positive feedback, which helps the circuit to reach the final separation of the output quickly. To meet the requirement of low voltage operation, CMOS technology is scaling down, but the problem is that the threshold voltage does not reduce in the same manner, which limits the scaling of the power supply. So, there is a need for some techniques or additional circuitry to reduce power consumption and able the latch to enter the regeneration phase fast. To operate ADCs at high frequency, one restriction is input signal range of the dynamic comparator. This thesis is a comprehensive exploration of high-performance dynamic comparator circuits and FLASH ADC architecture. At the core of this endeavor lies the integration of state-of-the-art simulation tools, prominently Cadence Virtuoso, to materialize circuitry that excels in both efficiency and reliability. The simulation of comparators are carried out using CMOS 90 nm and 180 nm technology with essential parameters voltage supply, maximum frequency, power dissipation, delay, energy efficiency, power delay product (PDP), Energy/conversion, Energy efficiency/conversion (EPC), slew rate, offset, and number of transistors. Apart from the aforementioned performance parameters comprehensive Monte Carlo analysis and process corner analysis were performed to ensure robustness under diverse operating conditions and manufacturing variations. By meticulously refining circuit designs and augmenting their power dissipation and delay, this research aims to make significant contributions to the ongoing evolution of ADCs architecture, ensuring its continued advancement and innovation in the realm of nanoscale technologies. Some special contributions made in this thesis are as follows: Innovative Architectures: The thesis introduces new designs for essential Analog components like : Dynamic Comparators FLASH ADC These designs are optimized to enhance performance metrics such as speed, power efficiency, and area utilization, catering to the evolving needs of high-performance analog and digital interfaces. Optimization Strategies: Novel optimization techniques are used to improve the efficiency and performance of digital circuit components. The dynamic comparator architecture is divided into two parts: one is the preamplifier stage, and another is the latch. So, there is the possibility of the implementation of some novel techniques at any stage of the dynamic comparator to improve delay and power dissipation. Charge Shared Technique: A PMOS (p-channel metal oxide semiconductor) placed between the outputs of the latch stage of the dynamic comparator provides the charge sharing during the reset phase. In the evaluation phase output terminal will not go below the threshold voltage, and the latch will be on at the start of the evaluation phase. Hence, the input signal can be compared faster during the regeneration phase, which speeds up the operation and reduces the delay. Latch Enhancement Technique: Changing the gate interconnection of transistors of the inverters existing in the latch stage which provides faster comparison and including extra transistors in the latch will help in reducing the power dissipation. Comparative Analysis: The thesis conducts comprehensive comparative analysis of this work with reported work. By identifying the strengths and weaknesses of different circuit architectures and transistor technologies, the thesis offers insights into the trade-offs involved in circuit optimization, guiding future research directions.